The present invention relates in general to integrated circuit packaging, and more specifically to an improved leadless plastic chip carrier which includes a unique die attach pad feature.
According to well known prior art IC (integrated circuit) packaging methodologies, semiconductor dice are singulated and mounted using epoxy or other conventional means onto respective die pads (attach paddles) of a leadframe strip. Traditional QFP (Quad Flat Pack) packages incorporate inner leads which function as lands for wire bonding the semiconductor die bond pads. These inner leads typically require mold locking features to ensure proper positioning of the leadframe strip during subsequent molding to encapsulate the package. The inner leads terminate in outer leads that are bent down to contact a mother board, thereby limiting the packaging density of such prior art devices.
In order to overcome these and other disadvantages of the prior art, the Applicants previously developed a Leadless Plastic Chip Carrier (LPCC). According to Applicants"" LPCC methodology, a leadframe strip is provided for supporting up to several hundred devices. Singulated IC dice are placed on the strip die attach pads using conventional die mount and epoxy techniques. After curing of the epoxy, the dice are gold wire bonded to peripheral internal leads. The leadframe strip is then molded in plastic or resin using a modified mold wherein the bottom cavity is a flat plate. In the resulting molded package, the die pad and leadframe inner leads are exposed. By exposing the bottom of the die attach pad, mold delamination at the bottom of the die attach pad (paddle) is eliminated, thereby increasing the moisture sensitivity performance. Also, thermal performance of the IC package is improved by providing a direct thermal path from the exposed die attach pad to the motherboard. By exposing the leadframe inner leads, the requirement for mold locking features is eliminated and no external lead standoff is necessary, thereby increasing device density and reducing package thickness over prior art methodologies. The exposed inner leadframe leads function as solder pads for motherboard assembly such that less gold wire bonding is required as compared to prior an methodologies, thereby improving electrical performance in terms of board level parasitics and enhancing package design flexibility over prior art packages (i.e. custom trim tools and form tools are not required). These and several other advantages of Applicants"" own prior art LPCC process are discussed in Applicants"" U.S. Pat. No. 6,229,200, issued May 8, 2001, the contents of which are incorporated herein by reference.
Applicants"" LPCC production methodology utilizes saw singulation to isolate the perimeter I/O row as well as multi-row partial lead isolation. Specifically, the leadframe strip is mounted to a wafer saw ring using adhesive tape and saws-singulated using a conventional wafer saw. The singulation is guided by a pattern of fiducial marks on the bottom side of the leadframe strip. Also, special mold processing techniques are used to prevent the mold flow from bleeding onto the functional pad area and inhibiting electrical contact. Specifically, the exposed die pad surface is required to be deflashed after molding to remove any molding compound residue and thereby allow the exposed leads and die attach pad to serve as solder pads for attachment to the motherboard.
According to Applicants"" co-pending U.S. patent application Ser. No. 09/288,352, the contents of which are incorporated herein by reference, a localized etch process is provided for the improved manufacture of the LPCC IC package. The leadframe strip is subjected to a partial etch on one or both of the top and bottom surfaces in order to create a pattern of contact leads (pads) and a die attach pad (paddle).
Although these prior art processes yield IC package designs with improved electrical performance over the prior art, it is desirable to further increase package density and thereby reduce the length of the gold wire bonds.
Accordingly, it is an object of the present invention to provide an improved leadless plastic chip carrier which includes a post mold etch back step and a unique die attach pad feature.
According to an aspect of the present invention, a new leadless plastic chip carrier is provided. The leadless plastic chip carrier has a die attach pad, a semiconductor die mounted to a portion of the die attach pad and at least one row of contact pads circumscribing the die attach pad. The contact pads have a thickness greater than the thickness of the portion of the die attach pad. A plurality of wire bonds connect the die attach pad and the contact pads and an overmold covers the semiconductor die and all except one surface of the contact pads and the die attach pad.
According to another aspect of the present invention, a new process for fabricating a leadless plastic chip carrier is provided. The process has the steps of: depositing a photo-imageable etch resist on opposing first and second surfaces of a leadframe strip; imaging and developing the etch resist to define a pattern for a die attach pad and at least one row of contact pads; etching the leadframe strip to define the contact pads and the die attach pad such that at least a portion of the die attach pad has a thickness less than the thickness of the contact pads; mounting the semiconductor die to the portion of the die attach pad; wire bonding the semiconductor die to the contact pads; and encapsulating the first surface of the leadframe strip in a molding material.
It is an advantage of an aspect of the present invention that the semiconductor die sits in a portion of the die attach pad that is reduced in thickness and therefore the length of the wire bonds (both to the die attach pad (ground bonds) and to the external pads (I/O bonds) can be reduced. Because electrical impedance in an IC package is directly related to the wire length, this construction allows for a LPCC package suitable to operate an higher frequencies compared to the prior art packages.
A further advantage of an aspect of the present invention is provided by the three dimensional nature of the partial etch die attach pad. This pad provides additional exposed metal for the mold compound to adhere to, thereby providing a more robust package.
Still further, it is an advantage of an aspect of the present invention that the die and wire bonds are lower in the profile of the package. This allows the option of using a thinner mold cap to further reduce the package profile.